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cy7c1325g 4-mbit (256 k 18) flow through sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05518 rev. *h revised march 29, 2011 4-mbit (256 k 18) flow through sync sram features 256 k 18 common i/o 3.3 v core power supply (v dd ) 2.5 v or 3.3 v i/o power supply (v ddq ) fast clock-to-output times 6.5 ns (133 mhz version) provide high performance 2-1-1-1 access rate user selectable burst counter supporting intel pentium interleaved or linear burst sequences separate processor and controller address strobes synchronous self timed write asynchronous output enable available in pb-free 100-pin tqfp package, pb-free and non pb-free 119-ball bga package ?zz? sleep mode option functional description the cy7c1325g [1] is a 256 k 18 synchronous cache ram designed to interface with high speed microprocessors with minimum glue logic. maximum a ccess delay from clock rise is 6.5 ns (133 mhz version). a 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw [a:b] , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. the cy7c1325g allows either interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). the cy7c1325g operates from a +3.3 v core power supply while all outputs may operate with either a +2.5 or +3.3 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. . address register adv clk burst counter and logic clr q1 q0 adsc ce 1 oe sense amps memory array adsp output buffers input registers mode ce 2 ce 3 gw bwe a 0,a1,a bw b bw a dq b ,dqp b write register dq a ,dqp a write register enable register a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control zz logic block diagram note 1. for best practice recommendations, refer to the cypress application note ? system design guidelines ? on www.cypress.com . [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 2 of 21 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 pin definitions .................................................................. 4 functional overview ........................................................ 6 single read accesses ................................................ 6 single write accesse s initiated by adsp ................... 6 single write accesses initiate d by adsc ................... 6 burst sequences ......................................................... 6 sleep mode ................................................................. 6 interleaved burst address table (mode = floating or vdd) ............................................... 7 linear burst address table (mode = gnd) .................. 7 zz mode electrical characteris tics ................................. 7 truth table ........................................................................ 8 truth table for read/write .............................................. 9 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics ............................................... 10 capacitance .................................................................... 11 thermal resistance ........................................................ 11 switching characteristics .............................................. 12 timing diagrams ............................................................ 13 ordering information ...................................................... 17 ordering code definitions ..... .................................... 17 package diagrams .......................................................... 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 21 worldwide sales and design s upport ......... .............. 21 products .................................................................... 21 psoc solutions ......................................................... 21 [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 3 of 21 selection guide description 133 mhz 100 mhz unit maximum access time 6.5 8.0 ns maximum operating current 225 205 ma maximum standby current 40 40 ma pin configurations figure 1. 100-pin tqfp pinout a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/9m a a a a a a a nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsp a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 byte a a adv adsc zz mode nc/18m nc byte b cy7c1325g [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 4 of 21 figure 2. 119-ball bga pinout pin definitions name i/o description a0, a1, a input- synchronous address inputs used to select one of the 256 k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the 2 bit counter. bw a, bw b input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are writte n, regardless of the values on bw [a:b] and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input-clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the directi on of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. pin configurations (continued) 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m nc dq b dq b dq b dq b aa aa adsp v ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc nc/72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc nc nc nc nc a a nc v ddq v ddq v ddq a nc/36m a a ce 3 a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a v ss bw b nc v dd nc bw a nc bwe v ss zz a [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 5 of 21 adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places th e device in a non-time-critical ?sleep? condition with data integrity preserved.during normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs dqp a, dqp b i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp [a:b] are placed in a tristate condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc no connects . not internally connected to the die. nc/9m, nc/18m, nc/36m, nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the die. nc/9m, nc/18m, nc/36m, nc/72m, nc/144m, nc/288m, nc/576m and nc/1g are address expansio n pins that are not in ternally connected to the die. pin definitions (continued) name i/o description [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 6 of 21 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133 mhz device). the cy7c1325g supports seconda ry cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 processors. the linear burst sequence is suited for proces sors that utilize a linear burst sequence. the burst order is user-selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw [a:b] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simp lified with on-chi p synchronous self timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address regist er and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data is available at the data outputs, a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into the address register and the burst inputs (gw , bwe , and bw [a:b] ) are ignored during this first clock cycle. if the write inputs are asserted active (see write cycle descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. byte writes are allowed. during byte writes, bw a controls dq a and bw b controls dq b . all i/os are tristated during a byte write.since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tristated prior to the presentation of data to dq s . as a safety precaution, the data lines are tristated after a write c ycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw [a:b] ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. the information presented to dq [a:d] is written into the specified address location. byte writes are allowed. during byte writes, bw a controls dq a , bw b controls dq b . all i/os are tristated when a write is detected , even a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tristated prior to the presen- tation of data to dq s . as a safety precaution, the data lines are tristated after a write cycle is de tected, regardless of the state of oe . burst sequences the cy7c1325g provides an on-chip two bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the stat e of the mode input. a low on mode selects a linear burst sequence. a high on mode selects an interleaved burst or der. leaving mode unconnected causes the device to default to a interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. 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cy7c1325g document number: 38-05518 rev. *h page 7 of 21 . interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a 1 , a 0 second address a 1 , a 0 third address a 1 , a 0 fourth address a 1 , a 0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 40 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ? ns [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 8 of 21 truth table the truth table for part cy7c1325g is as follows. [2, 3, 4, 5, 6] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power-down none h x x l x l x x x l-h tri-state deselected cycle, power-down none l l x l l x x x x l-h tri-state deselected cycle, power-down none l x h l l x x x x l-h tri-state deselected cycle, power-down none l l x l h l x x x l-h tri-state deselected cycle, power-down none x x x l h l x x x l-h tri-state sleep mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes 2. x = ?don?t care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals (bw a , bw b ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b ), bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a: b] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tristate. oe is a don't care for the remainde r of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tristate when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 9 of 21 truth table for read/write the truth table for read/write for part cy7c1325g is as follows. [7] function gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x note 7. x = ?don?t care.? h = logic high, l = logic low. [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 10 of 21 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature... ............... ............... ?65 c to +150 c ambient temperature with power applied ............. ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd ........?0.5 v to +4.6 v supply voltage on v ddq relative to gnd....... ?0.5 v to +v dd dc voltage applied to outputs in tristate ............................................?0.5 v to v ddq + 0.5 v dc input voltage .................................. ?0.5 v to v dd + 0.5 v current into outputs (low) ......................................... 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature ] v dd v ddq commercial 0 c to +70 c 3.3 v ??? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single bit upsets 25 c 361 394 fit/ mb lmbu logical multi bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to application note an 54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates? electrical characteristics over the operating range [8, 9] parameter description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [8] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ? 55 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq , output disabled ?5 5 ? a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 7.5 ns cycle, 133 mhz ? 225 ma 10 ns cycle, 100 mhz ? 205 ma notes 8. overshoot: v ih (ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2 v (pulse width less than t cyc /2). 9. t power up : assumes a linear ramp from 0 v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd. [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 11 of 21 i sb1 automatic ce power-down current?ttl inputs max v dd , device deselected, v in ? v ih or v in ? v il , f = f max , inputs switching 7.5 ns cycle, 133 mhz ? 90 ma 10 ns cycle, 100 mhz ? 80 ma i sb2 automatic ce power-down current?cmos inputs max v dd , device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 40 ma i sb3 automatic ce power-down current?cmos inputs max v dd , device deselected, v in ? v ddq ? 0.3 v or v in ? 0.3 v, f = f max , inputs switching 7.5 ns cycle, 133 mhz ? 75 ma 10 ns cycle, 100 mhz ? 65 ma i sb4 automatic ce power-down current?ttl inputs max v dd , device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 45 ma capacitance [10] parameter description test conditions 100-pin tqfp max 119-ball bga max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 3.3 v 55pf c clk clock input capacitance 5 5 pf c i/o input/output capacitance 5 7 pf thermal resistance [10] parameter description test conditions 100 tqfp package 119 bga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 30.32 34.1 c/w ? jc thermal resistance (junction to case) 6.85 14.0 c/w electrical characteristics (continued) over the operating range [8, 9] parameter description test conditions min max unit figure 3. ac test loads and waveforms note 10. tested initially and after any design or process change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 12 of 21 switching characteristics over the operating range [11, 12] parameter description ?133 ?100 unit min max min max t power v dd (typical) to the first access [13] 1?1?ms clock t cyc clock cycle time 7.5 ? 10 ? ns t ch clock high 2.5 ? 4.0 ? ns t cl clock low 2.5 ? 4.0 ? ns output times t cdv data output valid after clk rise ? 6.5 ? 8.0 ns t doh data output hold after clk rise 2.0 ? 2.0 ? ns t clz clock to low z [14, 15, 16] 0?0?ns t chz clock to high z [14, 15, 16] ?3.5?3.5ns t oev oe low to output valid ? 3.5 ? 3.5 ns t oelz oe low to output low z [14, 15, 16] 0?0?ns t oehz oe high to output high z [14, 15, 16] ?3.5?3.5ns setup times t as address setup before clk rise 1.5 ? 2.0 ? ns t ads adsp , adsc setup before clk rise 1.5 ? 2.0 ? ns t advs adv setup before clk rise 1.5 ? 2.0 ? ns t wes gw , bwe , bw x setup before clk rise 1.5 ? 2.0 ? ns t ds data input setup before clk rise 1.5 ? 2.0 ? ns t ces chip enable setup 1.5 ? 2.0 ? ns hold times t ah address hold after clk rise 0.5 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.5 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.5 ? 0.5 ? ns t advh adv hold after clk rise 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? 0.5 ? ns notes 11. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 12. test conditions shown in (a) of figure 3 on page 11 unless otherwise noted. 13. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 14. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 3 on page 11 . transition is measured 200 mv from steady-state voltage. 15. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus c ontention condition, but reflect parameters g uaranteed over worst case user conditions . device is designed to achieve high z prior to low z under the same system conditions. 16. this parameter is sampled and not 100% tested. [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 13 of 21 timing diagrams figure 4. read cycle timing [17] note 17. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle dont care undefined adsp adsc g w, bwe,bw [a:b] ce adv oe [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 14 of 21 figure 5. write cycle timing [18, 19] notes 18. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 19. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:b] low. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined adsp adsc bwe, bw [a:b] gw ce adv oe data in (d) d ata out (q) [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 15 of 21 figure 6. read/write timing [20, 21, 22] notes 20. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 21. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 22. gw is high. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes dont care undefined adsp adsc bwe, bw [a:b] ce adv oe data in (d) data out (q) [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 16 of 21 figure 7. zz mode timing [23, 24] notes 23. device must be deselected when entering zz mode. see cycle desc riptions table for all possible signal conditions to deselect the device. 24. dqs are in high z when exiting zz sleep mode. timing diagrams (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 17 of 21 ordering information the table below contains only the parts that are currently availa ble. if you don?t see what you are looking for, please contact your local sales representative. for more informa tion, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices speed (mhz) ordering code package diagram part and package type operating range 133 CY7C1325G-133AXC 51-85050 100-pin thin quad flat pack (14 20 1.4 mm) pb-free commercial ordering code definitions temperature range: c = commercial package type: ax = 100-pin tqfp (pb-free) speed grade: 133 mhz process technology ? 90nm 1325 = ft, 256 kb 18 (4 mb) marketing code: 7c = srams company id: cy = cypress c 7c 1325 g - 133 ax cy [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 18 of 21 package diagrams figure 8. 100-pin tqfp (14 20 1.4 mm), 51-85050 figure 9. 119-ball bga (14 22 2.4 mm), 51-85115 51-85050 *d 51-85115 *c [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 19 of 21 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor ce chip enable cen clock enable i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes mm milli meter ms milli seconds mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
cy7c1325g document number: 38-05518 rev. *h page 20 of 21 document history page document title: cy7c1325g, 4-mbit (256 k 18) flow through sync sram document number: 38-05518 revision ecn orig. of change submission date description of change ** 224366 rkf see ecn new datasheet *a 283775 vbl see ecn deleted 66 mhz changed tqfp package to pb-free tqfp in ordering information section added bg pb-free package *b 333626 syt see ecn removed 117 mhz speed bin modified address expansion balls in the pinouts for 100 tqfp and 119 bga packages as per jedec standards and updated the pin definitions accordingly modified v ol, v oh test conditions replaced ?snooze? with ?sleep? replaced tbd?s for ? ja and ? jc to their respective values on the thermal resistance table changed the package name for 100 tqfp from a100ra to a101 removed comment on the availability of bg pb-free package updated the ordering information by s hading and unshading mpns as per availability *c 418633 rxu see ecn converted from preliminary to final changed address of cypress semiconducto r corporation on page# 1 from ?3901 north first street? to ?198 champion court? modified test condition in footnote from v ddq < v dd to v ddq < v dd modified ?input load? to ?input leakag e current except zz and mode? in the electrical characteristics table. replaced package name column with package diagram in the ordering infor- mation table replaced package diagram of 51-85050 from *a to *b updated the ordering information *d 480124 vkn see ecn added the maximum rating for supply voltage on v ddq relative to gnd. updated the ordering information table. *e 2756998 vkn 08/28/09 included soft error immunity data modified ordering information table by including parts that are available and modified the disclaimer for the ordering information. *f 3036073 njy 09/22/2010 added ordering code definitions . updated package diagrams . added acronyms and units of measure . minor edits and updated in new template. *g 3052903 njy 10/08/10 removed the following prun ed part from the ordering information table. cy7c1325g-100axi *h 3208774 njy 03/29/2011 updated ordering information . updated package diagrams . [+] feedback
document number: 38-05518 rev. *h revised march 29, 2011 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1325g ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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